
/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 3.2.2 EDK_Cm.22
* DO NOT EDIT.
*
* Copyright (c) 2003 Xilinx, Inc.  All rights reserved. 
* 
* Description: Driver parameters
*
*******************************************************************/

#define XPAR_XGPIO_NUM_INSTANCES 2
#define XPAR_MYGPIO_BASEADDR 0xFFFE0100
#define XPAR_MYGPIO_HIGHADDR 0xFFFE01FF
#define XPAR_MYGPIO2_BASEADDR 0xFFFE0A00
#define XPAR_MYGPIO2_HIGHADDR 0xFFFE0AFF

/******************************************************************/

#define XPAR_XUARTLITE_NUM_INSTANCES 1
#define XPAR_MYUART_BASEADDR 0xFFFE0200
#define XPAR_MYUART_HIGHADDR 0xFFFE02FF

/******************************************************************/

#define XPAR_MYPLBBRAM_CNTLR_BASEADDR 0xFFFF0000
#define XPAR_MYPLBBRAM_CNTLR_HIGHADDR 0xFFFF3FFF
#define XPAR_MYPLBBRAM_CNTLR1_BASEADDR 0xFFFFC000
#define XPAR_MYPLBBRAM_CNTLR1_HIGHADDR 0xFFFFFFFF
#define XPAR_INST_PLB_SDRAM_BASEADDR 0x00000000
#define XPAR_INST_PLB_SDRAM_HIGHADDR 0x01FFFFFF

/******************************************************************/

#define STDIN_BASEADDRESS 0xFFFE0200
#define STDOUT_BASEADDRESS 0xFFFE0200
#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 400000000
